The present invention relates to a semiconductor device, and, more particularly, to a technique which is effectively applicable to a semiconductor device in which bonding pads of a semiconductor chip are connected to connecting portions which are arranged around the semiconductor chip using bonding wires.
Semiconductor devices having various package structures, which differ depending on the functions and kinds of integrated circuits mounted on a semiconductor chip, have been commercialized. As one example of these semiconductor devices, there is a semiconductor device which is referred to as a QFP (Quad Flatpack Package) type semiconductor device. The QFP type semiconductor device is mainly constituted of a semiconductor chip having a main surface on which a plurality of bonding pads and a plurality of buffer cells are arranged, a plurality of leads arranged around the semiconductor chip, a plurality of bonding wires which electrically connect the plurality of the bonding wires of the semiconductor chip and the plurality of leads, respectively, support bodies (tabs, die pads) provided for supporting the semiconductor chips, suspending leads which are integrally formed with the support bodies, and a sealing body which seals the semiconductor chip, the plurality of bonding wires, and inner lead portions of the plurality of leads.
The plurality of bonding pads include a plurality of signal bonding pads and a plurality of power source bonding pads, and then are arrange along respective sides of the semiconductor chip. The plurality of buffer cells include a plurality of input-output cells (I/O cells) and a plurality of power source cells, wherein the plurality of input-output cells are arranged at locations corresponding to the plurality of respective signal bonding pads and the plurality of power source cells are arranged at locations corresponding to the plurality of respective power source bonding pads. The plurality of leads include a plurality of signal leads and a plurality of power source leads, wherein the plurality of signal leads are arranged at locations corresponding to the plurality of respective signal bonding pads and the plurality of power source leads are arranged at locations corresponding to the plurality of respective power source bonding pads.
A technique for respectively electrically connecting the plurality of bonding pads of the semiconductor chip with the plurality of leads arranged around the semiconductor chip is described in Japanese Unexamined Patent Publication Hei 6(1994)-283604, for example.
[Patent Reference 1]
Japanese Unexamined Patent Publication Hei 6(1994)-283604